After an interrupt service routine finishes, the system often runs the scheduler to decide what to execute next. In a preemptive system, an ISR can wake up or unblock a higher-priority task. When the ISR returns, the scheduler sees that a higher-priority task is now ready and performs a context switch to that task, saving the state of the current task and loading the state of the higher-priority one. This is why a context switch after an ISR is possible and often expected: the interrupt may reveal more urgent work that should run immediately. This isn’t guaranteed to always resume the interrupted task, because if a higher-priority task became ready during the ISR, the scheduler will switch to that task. It’s also not accurate to say there’s no context switch after an ISR in a system with preemption, since the exit from the ISR is precisely when the scheduler decides whether a switch is needed. The idea that the interrupt preempts the current thread until it completes is a misunderstanding of how scheduling and ISR handling interact: the ISR runs, then the scheduler decides if a higher-priority task should run next, which can involve a context switch.

Primary storage is the fast, directly usable memory the CPU uses while executing programs. It is typically volatile, meaning it loses data when power is removed. This category includes the CPU’s registers, the caches (L1/L2/L3), and RAM. These memory types are designed for very low latency access to the instructions and data the processor is actively working with. In contrast, non-volatile storage like HDDs, SSDs, optical disks, external SAMPLEcloud storage, or tape is used for long-term persistence and backup, not for the immediate, high-speed work of the CPU. So the correct idea is that primary storage consists of volatile, quickly accessible memory areas such as registers, RAM, and cache.

During boot, firmware on the motherboard (the BIOS) initializes hardware, performs a short self-test, and then locates a bootable device. It loads the initial bootstrap code from that device into RAM and transfers control to it. That bootstrap loader is responsible for loading the operating system into memory so it can run. In this sense, the BIOS participates in bringing the OS into RAM to start it by moving the boot code into memory and handing off execution to it, which ultimately leads to the OS kernel being loaded into RAM. The other statements describe actions that aren’t what BIOS does during the boot process: it doesn’t load user programs directly at boot, it doesn’t run the OS kernel before configuring BIOS settings, and it doesn’t format the hard drive.

PCIe uses a scalable, high-speed serial interface. The xN notation shows how many physical lanes form one link. Each lane is a separate serial channel, and the lanes operate in parallel to boost total bandwidth. So x16 means sixteen lanes are bonded to work together as a single PCIe link, giving much more bandwidth than a single lane. The actual speed per lane depends on the PCIe generation (Gen 3, Gen 4, Gen 5), but the core idea is that sixteen lanes are used together to carry data. This is different from a 16-bit data path, since PCIe lanes carry serial data, not a single wide 16-bit parallel bus. A single data channel describes a single-lane link, which is not what x16 represents.